Design of a High Efficiency DC–DC Buck Converter With Two-Step Digital PWM and Low Power Self-Tracking Zero Current Detector for IoT Applications

• Published in: IEEE transactions on power electronics Vol. 33; no. 2; pp. 1428 - 1439
• Main Authors: Kim, Sang-Yun, Hwang, Keum Cheol, Yang, Youngoo, Lee, Kang-Yoon, Park, Young-Jun, Ali, Imran, Nga, Truong Thi Kim, Ryu, Ho-Cheol, Khan, Zaffar Hayat Nawaz, Park, Seong-Mun, Pu, Young Gun, Lee, Minjae
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.02.2018; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adaptive control; Adaptive window analog to digital converter (ADC); Analog to digital converters; Buck converters; CMOS; dc–dc buck converter; Delay; Delay lines; Delays; digital compensator; digital pulse width modulation (DPWM); Efficiency; Electric potential; Energy conversion efficiency; hybrid digital pulse width modulation core; Hybrid power systems; Internet of Things; Linearity; Power consumption; Power demand; Pulse duration; Pulse duration modulation; self-tracking zero current detector (ST-ZCD); Tracking
• ISSN: 0885-8993; 1941-0107
• DOI: 10.1109/TPEL.2017.2688387

In this paper, a high efficiency dc-dc buck converter with two-step digital pulse width modulation (DPWM) and low power self-tracking zero current detector (ST-ZCD) is proposed for Internet of Things (IoT) and ultralow power applications. The hybrid DPWM core with high linearity and low power consumption is proposed to implement the high efficiency DPWM dc-dc converter. It is composed of a two-step delay control using the counter and delay line. An adaptive window analog to digital converter is proposed to reduce the output voltage ripple within 20 mV. A dead time generator is implemented with the proposed ST-ZCD to minimize the reverse current. The ST-ZCD can improve efficiency by reducing the control loss that accounts for a large proportion of the dc-dc converter. Also, all digital type-III compensator is implemented for the low power and small die area. This chip is fabricated with a 55 nm CMOS process, which uses the standard supply voltage of 1.5-3 V to generate the output voltage of 1.2 V. The total active area is 500 μm × 300 μm. The measured peak efficiency of the DPWM dc-dc buck converter is 91.5% with a quiescent current consuming only 130 μA.