A Dual-Junction Single-Photon Avalanche Diode in 130-nm CMOS Technology
A dual-junction single-photon avalanche diode structure is reported in a 130-nm low-voltage CMOS technology. The device comprises two stacked avalanche multiplication regions with virtual guard ring constructions. An 8.6- μm-diameter p-well is placed within a 12.3- μm-diameter deep n-well. At 3-V ex...
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Published in | IEEE electron device letters Vol. 34; no. 3; pp. 429 - 431 |
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Main Authors | , , |
Format | Journal Article |
Language | English |
Published |
New York, NY
IEEE
01.03.2013
Institute of Electrical and Electronics Engineers |
Subjects | |
Online Access | Get full text |
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Summary: | A dual-junction single-photon avalanche diode structure is reported in a 130-nm low-voltage CMOS technology. The device comprises two stacked avalanche multiplication regions with virtual guard ring constructions. An 8.6- μm-diameter p-well is placed within a 12.3- μm-diameter deep n-well. At 3-V excess bias, the junctions operate with median dark count rates of 10 and 5 kHz and photon detection efficiencies of 32% at 450 nm and 29% at 670 nm, respectively. We demonstrate that the junction at which a photon is detected can be uniquely distinguished by the dead time of the Geiger mode pulse allowing spectral discrimination by simple digital circuitry. |
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ISSN: | 0741-3106 1558-0563 |
DOI: | 10.1109/LED.2012.2236816 |