A 17.7-19.2-GHz Receiver Front End With an Adaptive Analog Temperature-Compensation Scheme

• Published in: IEEE transactions on microwave theory and techniques Vol. 71; no. 3; pp. 1 - 15
• Main Authors: Li, Min, Gao, Huiyan, Li, Nayu, Wang, Shaogang, Zhang, Zijiang, Chen, Peidi, Wei, Ningjie, Yu, Xiaopeng, Gu, Qun Jane, Song, Chunyi, Xu, Zhiwei
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.03.2023; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: <inline-formula xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> <tex-math notation="LaTeX"> K</tex-math> </inline-formula>-band; Adaptive control; Adaptive gain control; Amplification; analog; Analog circuits; beamforming; Calibration; Circuit design; CMOS; Gain; low-power multibeam phased array; Noise levels; Phase error; Phased arrays; Power consumption; Power gain; receiver front end; Receivers; Temperature compensation; Temperature measurement; Temperature sensors; Transistors; Variable gain; variable-gain amplifier
• ISSN: 0018-9480; 1557-9670
• DOI: 10.1109/TMTT.2022.3215558

This article presents an eight-element 17.719.2-GHz receiver front end with 12 concurrent beams in a 65-nm CMOS technology. Each output beam utilizes a temperature-compensation variable-gain amplifier (TC-VGA) to minimize the temperature-induced gain variation. The concept of the proposed TC-VGA and the realization of corresponding adaptive analog control are introduced in detail. The front-end architecture and circuit-level design to enable a flat wideband gain response, precise phase and amplitude control, low power consumption, and adaptive analog temperature compensation are presented. Wafer probing is conducted to measure the performance of the receiver front end. The measured gain-temperature coefficient is <inline-formula> <tex-math notation="LaTeX">\pm</tex-math> </inline-formula>0.005 dB/<inline-formula> <tex-math notation="LaTeX">^\circ</tex-math> </inline-formula>C from <inline-formula> <tex-math notation="LaTeX">-</tex-math> </inline-formula>15<inline-formula> <tex-math notation="LaTeX">^\circ</tex-math> </inline-formula>C to 85 <inline-formula> <tex-math notation="LaTeX">^\circ</tex-math> </inline-formula>C at 17.719.2 GHz, while the counterpart without temperature compensation is <inline-formula> <tex-math notation="LaTeX">-</tex-math> </inline-formula>0.1 dB/<inline-formula> <tex-math notation="LaTeX">^\circ</tex-math> </inline-formula>C. The chip demonstrates a 28-dB power gain, a 26% 3-dB fractional bandwidth, a 3.24.1-dB noise figure (NF), and a <inline-formula> <tex-math notation="LaTeX">-</tex-math> </inline-formula>27.4-dBm input 1-dB gain compression point (IP<inline-formula> <tex-math notation="LaTeX">_{\mathrm{1\,dB}}</tex-math> </inline-formula>) for each element. In addition, each channel provides 7-bit phase-shifting resolution and 6-bit attenuation for a 15.75-dB gain range with a <inline-formula> <tex-math notation="LaTeX"><</tex-math> </inline-formula>1.5<inline-formula> <tex-math notation="LaTeX">^\circ</tex-math> </inline-formula> root-mean-square (rms) phase error, and a <inline-formula> <tex-math notation="LaTeX"><</tex-math> </inline-formula>0.22-dB rms amplitude error. The chip occupies 4.65 <inline-formula> <tex-math notation="LaTeX">\times</tex-math> </inline-formula> 2.77 mm<inline-formula> <tex-math notation="LaTeX">^2</tex-math> </inline-formula> area with pads, equivalent to 1.61 mm<inline-formula> <tex-math notation="LaTeX">^2</tex-math> </inline-formula> per element (for two beams), and consumes 37.2 mW per element per beam. To the best of our knowledge, the receiver front end demonstrates the minimum gain variation with temperature among silicon RF-beamforming front ends.