Modeling Random Clock Jitter Effect of High-Speed Current-Steering NRZ and RZ DAC

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 65; no. 9; pp. 2832 - 2841
• Main Authors: Kim, Seonggeon, Lee, Kang-Yoon, Lee, Minjae
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.09.2018; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Clocks; Computer simulation; current-steering (CS); Digital to analog conversion; Digital to analog converters; Digital-to-analog converter (DAC); Error analysis; High pass filters; high-pass filter (HPF); Jitter; low-pass filter (LPF); Mathematical model; Matlab; Noise prediction; Optical signal processing; random clock jitter; return-to-zero (RZ); Signal to noise ratio; signal-to-noise ratio (SNR); Steering; Timing; Vibration; White noise
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2018.2821198

In this paper, signal-to-noise ratio (SNR) degradation from random clock jitter in a current-steering digital-to-analog converter (CS-DAC) is analyzed based on a timing-to-amplitude error conversion method. A closed-form equation is derived to predict SNR for white noise clock jitter (WN-J) and low-pass filtered clock jitter (LPF-J) in non-return-to-zero (NRZ) and return-to-zero (RZ) DAC. Especially for the clock source with LPF-J, our equation predicts that the return-to-zero (RZ) DAC SNR is better than what the conventional analysis foresees due to the high-pass filter function derived in our analysis. Our analysis completely captures both WN-J and LPF-J in NRZ and RZ DAC, and is verified in both MATLAB simulation and measurement with the difference of less than 2 dB.