A Dual-Rail Hybrid Analog/Digital Low-Dropout Regulator With Dynamic Current Steering for a Tunable High PSRR and High Efficiency

• Published in: IEEE solid-state circuits letters Vol. 3; pp. 526 - 529
• Main Authors: Liu, Xiaosen, Krishnamurthy, Harish K., Barrera, Claudia, Han, Jing, Narayana Bhatla, Rajasekhara M., Chiu, Scott, Ahmed, Zakir K., Desai, Nachiket, Ravichandran, Krishnan, Tschanz, James W., De, Vivek
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: CMOS; Dual-rail; Efficiency; Energy conversion efficiency; heterogeneous integration; low-dropout regulator (LDO); multichip package (MCP); power-supply rejection ratio (PSRR); Rails; Regulators; Rejection; Semiconductor device measurement; Solid state circuits; Steering mechanisms; System-on-chip; Topology; Voltage control
• ISSN: 2573-9603; 2573-9603
• DOI: 10.1109/LSSC.2020.3035675

A dual-rail hybrid analog/digital low-dropout regulator (DRLDO) targeting heterogeneous integration in a multichip package (MCP) platform is presented. Different from the classic single-input-single-output low-dropout regulator (LDO) topology, which incurs an efficiency penalty due to a large dropout voltage, this DRLDO architecture breaks the tradeoff of power-supply rejection and high efficiency by exploiting two rails available in a typical MCP system on a chip. One rail is the larger dropout ac branch rail which helps with power-supply rejection while the other is the low-dropout dc branch that helps with maximizing efficiency. The hybrid combination of analog and digital branches achieves both high efficiency and high power-supply rejection ratio (PSRR) simultaneously. Moreover, a dynamic current steering mechanism actively regulates the current contribution between the two rails and flexibly tunes the PSRR and power conversion efficiency performances. Measurements on a 22-nm CMOS chip demonstrate up to −46-dB PSRR and 89% efficiency across a 0-80-mA load from 1.8-V HV and 1.05-V LV dual-input rails. It improves the efficiency of the conventional analog LDO (ALDO) in MCP applications up to 32% while still maintaining −20-dB PSRR performance.