A Common Core Model for Junctionless Nanowires and Symmetric Double-Gate FETs

• Published in: IEEE transactions on electron devices Vol. 60; no. 12; pp. 4277 - 4280
• Main Authors: Sallese, Jean-Michel, Jazaeri, Farzan, Barbut, Lucian, Chevillon, Nicolas, Lallement, Christophe
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.12.2013; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Cross-disciplinary physics: materials science; rheology; Doping; Double gate (DG); Electronics; enhancement mode; Exact sciences and technology; field effect transistor (FET); junctionless; Logic gates; Materials science; Mobile communication; modeling; Nanoscale materials and structures: fabrication and characterization; Nanowires; nanowires (NWs); Physics; Quantum wires; Semiconductor device modeling; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Semiconductor process modeling; Silicon; Transistors; Boltzmann equation; nanowires (NWs); field effect transistor (FET); Poisson equation; Compact design; Mismatching; Cylindrical shape; Modeling; Enhancement mode; Field effect transistor; Long channel; Junctionless transistor; Unification; junctionless; Nanowires; Double gate (DG); Dual gate field effect transistor; Planar technology
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2013.2287528

In this paper, we evidence the link between the planar and cylindrical junctionless field effect transistors (JL-FETs) from the electrostatics and current point of view. In particular, we show that an approximate solution of the Poisson-Boltzmann equation for JL nanowires can be mapped on the planar double-gate topology generating only negligible mismatch, meaning that both devices can share the same core model as far as long channels are considered. These preliminary results are a first step toward a unification of compact models for JL-FETs.