A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation

• Published in: IEEE journal of solid-state circuits Vol. 57; no. 6; pp. 1712 - 1722
• Main Authors: Kim, Hyojun, Jung, Woosong, Kim, Kwandong, Kim, Sungwoo, Choi, Woo-Seok, Jeong, Deog-Kyoon
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.06.2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: All-digital phase-locked loop (ADPLL); Calibration; Clocks; Closed loops; closed-loop system; Compensation; digitally controlled resistor (DCR); Frequency modulation; High gain; Jitter; multi-phase clock; Phase locked loops; phase noise; Power consumption; ring oscillator (RO); Robustness; supply noise; Transfer functions; Vibration; Voltage; voltage headroom
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2022.3148174

This article presents a ring oscillator (RO)-based all-digital phase-locked loop (ADPLL) that is implemented with a high-gain analog closed loop for supply noise compensation (ACSC). The ACSC not only allows high-frequency oscillation of the RO but also is robust over process, voltage, and temperature (PVT) variations thanks to its replica-based configuration. Moreover, a comprehensive analysis of the noise contribution of the ACSC is conducted for the ADPLL to retain its low-jitter output. Implemented in 40-nm CMOS technology, the ADPLL, with a 1.1-V supply, achieves an rms jitter of 289 fs at 8 GHz without any injected supply noise. Under a 20-<inline-formula> <tex-math notation="LaTeX">\text{m}\textrm {V}_{\textrm {rms}} </tex-math></inline-formula> white supply noise, the ADPLL gives rms jitters of 8.7 and 0.63 ps at 8 GHz when the ACSC is disabled and enabled, respectively. The overall power consumption and the area of the presented ADPLL are 9.48 mW and 0.055 <inline-formula> <tex-math notation="LaTeX">\textrm {mm} {^{\mathrm{ 2}}} </tex-math></inline-formula>, respectively.