A High-Density Metal-Fuse Technology Featuring a 1.6 V Programmable Low-Voltage Bit Cell With Integrated 1 V Charge Pumps in 22 nm Tri-Gate CMOS
The first metal-fuse technology in 22 nm tri-gate high-k metal-gate CMOS technology is presented. The memory technology offerings in high-volume manufacturing include a 2.05 μm 2 2.2 V programmable high-density and a 16.4 μm 2 1.6 V programmable low-voltage (LV) 1T1R bit cell. The LV operability of...
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Published in | IEEE journal of solid-state circuits Vol. 51; no. 4; pp. 1003 - 1008 |
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Main Authors | , , , , , |
Format | Journal Article |
Language | English |
Published |
New York
IEEE
01.04.2016
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subjects | |
Online Access | Get full text |
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Summary: | The first metal-fuse technology in 22 nm tri-gate high-k metal-gate CMOS technology is presented. The memory technology offerings in high-volume manufacturing include a 2.05 μm 2 2.2 V programmable high-density and a 16.4 μm 2 1.6 V programmable low-voltage (LV) 1T1R bit cell. The LV operability of the technology allows the fuse arrays to be coupled with power delivery circuits operating at standard logic voltage levels. A charge pump voltage doubler operating on a 1 V voltage rail is demonstrated in this paper with healthy fusing yield. |
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ISSN: | 0018-9200 1558-173X |
DOI: | 10.1109/JSSC.2015.2507786 |