Diagnosis of Intermittent Scan Chain Faults Through a Multistage Neural Network Reasoning Process

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 39; no. 10; pp. 3044 - 3055
• Main Authors: Chern, Mason, Lee, Shih-Wei, Huang, Shi-Yu, Huang, Yu, Veda, Gaurav, Tsai, Kun-Han, Cheng, Wu-Tung
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.10.2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Accuracy; Affine transformations; Artificial neural networks; Chains; Circuit faults; Diagnostic systems; Fault diagnosis; Indexes; Inference; Integrated circuits; intermittent faults; Learning theory; neural network; Neural networks; Neurons; stuck-at faults; Training
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2019.2957356

Diagnosis of intermittent scan chain failures still remains a hard problem. In this article, we demonstrate that the use of artificial neural networks (ANNs) can lead to significantly higher accuracy. The key of this method is a multistage process incorporating ANNs with gradually refined focuses. During this process, the final fault suspect is elected through multiple rounds of ANN inference, instead of just one round. At each stage, identification of a proper Affine Group , used as the "candidate set of scan cells for the next round of ANN inference," will influence the final diagnostic accuracy. Thus, we propose a validation-based learning procedure for Affine Group derivation to further boost the final diagnostic accuracy. The experimental results on benchmark circuits have shown that this method is, on the average, 17.46% more accurate than a state-of-the-art commercial tool for intermittent stuck-at-0 faults.