On-Chip Trust Evaluation Utilizing TDC-Based Parameter-Adjustable Security Primitive

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 40; no. 10; pp. 1985 - 1994
• Main Authors: Ma, Haocheng, He, Jiaji, Liu, Yanjiang, Kuai, Jun, Li, He, Liu, Leibo, Zhao, Yiqiang
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.10.2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Converters; Data analysis; Field programmable gate arrays; Field-programmable gate array (FPGA); Hardware; hardware trojan (HT); Integrated circuits; IP networks; Monitoring; on-chip detection; Parameters; principal component analysis (PCA); Security; System-on-chip; time-to-digital converter (TDC); Trustworthiness
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2020.3035346

Field-programmable gate arrays (FPGAs) are integrated circuits (ICs) that can be reconfigured to the desired functionalities, without manufacturing dedicated chips. Due to their programmable nature, FPGAs have been prevalent in the large majority of modern systems. This raises high demands for verifying the security of circuit implementations on FPGAs, since they are vulnerable to hardware trojans (HTs) that can be inserted through modified configuration files. In this article, we propose an on-chip security framework to ensure the trustworthiness of circuit implementations on FPGAs at runtime. The core of the framework is a time-to-digital converter (TDC)-based hardware security primitive that can be predeployed on FPGAs to verify whether the FPGA-based designs are tampered with or corrupted by HTs. The parameter-adjustable TDC sensor, which is the primary component of the primitive, is carefully designed, adjusted, and implemented, thus the TDC sensor can monitor the transient voltage fluctuations within FPGAs with a high resolution. Versus statistical data analysis, tiny abnormal variations introduced by the Trojan insertion and activation are distinguished. Experimental results on Xilinx Spartan-6 FPGAs demonstrate the effectiveness of the proposed TDC-based on-chip trust evaluation framework and HT detection method.