A Binary-Feature-Based Object Recognition Accelerator With 22 M-Vector/s Throughput and 0.68 G-Vector/J Energy-Efficiency for Full-HD Resolution

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 38; no. 7; pp. 1265 - 1277
• Main Authors: Liu, Leibo, Zhu, Wenping, Yin, Shouyi, Wei, Shaojun
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.07.2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Approximate nearest neighbor (ANN); binary feature; Cluster analysis; Clustering; CMOS; Feature extraction; Feature recognition; Forest management; Frequency modulation; Hardware; multisegment; Object recognition; Power consumption; Power efficiency; processing array; Search problems; State of the art; Vegetation; Vocabulary
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2018.2846634

Considering that the binary-feature-based approximate nearest neighbor (ANN) search technique has not been fully exploited to date, a multisegment binary feature-based hierarchical clustering tree model is proposed to achieve fast binary feature matching (FM). In addition, the multisegment vocabulary forest, is developed for the ease of hardware-oriented implementation. During the ANN searching process, the corresponding leaf nodes of each segment of the query feature are returned simultaneously to improve processing speed and accuracy. Furthermore, a hierarchical decomposition based on the term frequency-inverse document frequency is used to reduce the run-time search space and total memory footprint for object database storage. Finally, a fine-grained feature-level fully pipelined object recognition accelerator is implemented based on a dedicated design between FM and object scoring. The performance of the proposed object recognition accelerator is evaluated based on TSMC 65 nm CMOS technology. The accelerator achieves 22 M-vec/s and <inline-formula> <tex-math notation="LaTeX">6.8 \boldsymbol \times 10^{\mathbf {8}} </tex-math></inline-formula> vec/J in throughput and energy efficiency for full-HD resolution, respectively; these results represent a <inline-formula> <tex-math notation="LaTeX">10.6\boldsymbol \times </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">9\boldsymbol \times </tex-math></inline-formula> improvement, respectively, relative to current state-of-the-art solutions. The average power consumption is 32.6 mW when operating at 200 MHz.