A Novel Architecture of Large Hybrid Cache With Reduced Energy

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 64; no. 12; pp. 3092 - 3102
• Main Authors: He, Jiacong, Callenes-Sloan, Joseph
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2017; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Buffer storage; Buffers; Cache memory; Computer architecture; DRAM cache; Dynamic random access memory; Energy; Hybrid cache; Optimization; Random access memory; Stacking; STT-RAM; Technology transfer; Three-dimensional displays; Through-silicon vias
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2017.2719000

Energy becomes an inevitable challenge when using a large die-stacking dynamic random access memory (DRAM) cache. Although emerging spin-transfer-torque-RAM (STT-RAM) technology can efficiently reduce the static energy of large cache, it cannot completely replace DRAM cache due to the high write energy of STT-RAM. Recently, researchers have observed that there are many redundant bits written in the row buffer and futile bits written back to STT-RAM cells, which do not change the cells' value but still cost high write energy. In this paper, we first design a large hybrid cache architecture with the DRAM region and the STT-RAM region to reduce the high static energy of DRAM cache. The selective write back to row buffer and selective write back to cell array optimizations are proposed to reduce high write energy of the STT-RAM region by removing the unnecessary bit-writes. Furthermore, we propose reuse distance-oriented data movement to reduce write operations in the STT-RAM region. Finally, we propose a novel tag design for the hybrid cache by moving all tag arrays to the STT-RAM region. The SPEC CPU2006 benchmarks show an average 28.3% energy reduction and 6.7% performance improvement for the write optimizations and 7.3% energy savings and 27.5% instructions per cycle speedups for the proposed tag design.