IC Pin Modeling and Mitigation of ESD-Induced Soft Failures

• Published in: IEEE transactions on electromagnetic compatibility Vol. 63; no. 2; pp. 375 - 383
• Main Authors: Maghlakelidze, Giorgi, Shen, Li, Gossner, Harald, Pommerenke, David, Kim, DongHyun
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.04.2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Circuit model; Current measurement; Design optimization; Electric potential; electrostatic discharge (ESD); Electrostatic discharges; Failure; Integrated circuit modeling; Mathematical models; Model testing; Pins; Product development; Prototyping; Pulse duration; Robustness; Robustness (mathematics); SEED; soft failure (SF); SPICE; Static electricity; Stress; Transmission line measurements; transmission line pulse (TLP); Transmission lines; Voltage; Waveforms

In this article, electrostatic discharge (ESD) induced soft failures (SFs) of a USB3 Gen1 device are investigated by direct transmission line pulse injection with varying pulsewidth, amplitude, and polarity to characterize the failure behavior of the interface and to create a SPICE model of the volt...