IC Pin Modeling and Mitigation of ESD-Induced Soft Failures

In this article, electrostatic discharge (ESD) induced soft failures (SFs) of a USB3 Gen1 device are investigated by direct transmission line pulse injection with varying pulsewidth, amplitude, and polarity to characterize the failure behavior of the interface and to create a SPICE model of the volt...

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Bibliographic Details
Published inIEEE transactions on electromagnetic compatibility Vol. 63; no. 2; pp. 375 - 383
Main Authors Maghlakelidze, Giorgi, Shen, Li, Gossner, Harald, Pommerenke, David, Kim, DongHyun
Format Journal Article
LanguageEnglish
Published New York IEEE 01.04.2021
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
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Summary:In this article, electrostatic discharge (ESD) induced soft failures (SFs) of a USB3 Gen1 device are investigated by direct transmission line pulse injection with varying pulsewidth, amplitude, and polarity to characterize the failure behavior of the interface and to create a SPICE model of the voltage and current waveform dependent failure thresholds. ESD protection by transient-voltage-suppression diodes is numerically simulated in several configurations. The results show viability of using well-established hard failure mitigation techniques for improving SF robustness. A good agreement between numerical simulation for optimized board design and measurements are achieved. A novel concept of SF system efficient ESD design is proposed and demonstrated to be effective for making decisions during early product development, in board designing and prototyping phase.
ISSN:0018-9375
1558-187X
DOI:10.1109/TEMC.2020.3011544