A Small-Size K-Band SPDT Switch Using Alternate CMOS Structure With Resonating Inductor Matching

A single-pole double-throw (SPDT) CMOS switch at 15-25 GHz is presented, which has a small size, low insertion losses, and high-power handling capabilities for both output nodes. It has an SPDT structure in which nMOS and pMOS are alternately used as series and shunt transistors. An inductor-matchin...

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Bibliographic Details
Published inIEEE microwave and wireless components letters Vol. 30; no. 11; pp. 1093 - 1096
Main Authors Park, Jinseok, Lee, Wonho, Hong, Songcheol
Format Journal Article
LanguageEnglish
Published IEEE 01.11.2020
Subjects
28-nm CMOS
<italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">K -band
CMOS
Inductors
Insertion loss
Logic gates
MOS devices
RF~switch
single-pole double-throw (SPDT)
Switches
Switching circuits
Transistors
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Summary:A single-pole double-throw (SPDT) CMOS switch at 15-25 GHz is presented, which has a small size, low insertion losses, and high-power handling capabilities for both output nodes. It has an SPDT structure in which nMOS and pMOS are alternately used as series and shunt transistors. An inductor-matching network is placed between two output nodes for input and output matching, which is also used to increase isolation by resonating out the off capacitances. The proposed SPDT switch is fabricated using a 28-nm CMOS process. It achieves an insertion loss of less than 1.9 dB from 15 to 25 GHz. The measured IP 0.2dB of two outputs is 17.4 and 18.3 dBm, respectively. It has an isolation of 25 dB at 20 GHz. The measured ON/OFF switching time is less than 2.3 ns. The proposed SPDT switch has a core area of only 0.02 mm 2 .
ISSN:1531-1309
1558-1764
DOI:10.1109/LMWC.2020.3026389