Compact Model for Carbon Nanotube Field-Effect Transistors Including Nonidealities and Calibrated With Experimental Data Down to 9-nm Gate Length

• Published in: IEEE transactions on electron devices Vol. 60; no. 6; pp. 1834 - 1843
• Main Authors: Jieying Luo, Lan Wei, Chi-Shuen Lee, Franklin, A. D., Ximeng Guan, Pop, E., Antoniadis, D. A., Wong, H. P.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.06.2013; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Carbon nanotube (CNT); carbon nanotube field effect transistor (CNFET); CNTFETs; contact resistance; Cross-disciplinary physics: materials science; rheology; Data models; direct source-to-drain tunneling; Electronics; Exact sciences and technology; Integrated circuit modeling; Logic gates; Materials science; Molecular electronics, nanoelectronics; Nanoscale materials and structures: fabrication and characterization; Nanotubes; Numerical models; Physics; Semiconductor device modeling; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Transistors; Tunneling; Parasitic behavior; Performance evaluation; Nanotube devices; carbon nanotube field effect transistor (CNFET); Spurious capacity; Electric stress; Tunnel effect; Carbon nanotubes; Contact resistance; Compact design; Optimization; Nanoelectronics; Field effect transistor; direct source-to-drain tunneling; Virtual reality; Carbon nanotube (CNT); Leakage current; Delay time; Miniaturization; Series resistance; Effective mass; Limiter; Non ideality
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2013.2258023

A semianalytical carbon nanotube field-effect transistor (CNFET) model based on the virtual-source model is presented, which includes series resistance, parasitic capacitance, and direct source-to-drain tunneling leakage. The model is calibrated with recent experimental data down to 9-nm gate length. Device performance of 22- to 7-nm technology nodes is analyzed. The results suggest that contact resistance is the key performance limiter for CNFETs; direct source-to-drain tunneling results in significant leakage due to low effective mass in carbon nanotubes and prevents further downscaling of the gate length. The design space that minimizes the gate delay in CNFETs subject to OFF-state leakage current ( I OFF ) constraints is explored. Through the optimization of the length of the gate, contact, and extension regions to balance the parasitic effects, the gate delay can be improved by more than 10% at 11- and 7-nm technology nodes compared with the conventional 0.7 × scaling rule, while the OFF-state leakage current remains below 0.5 μA/μm .