Device-Circuit Co-design for Beyond 1 GHz 5 V Level Shifter Using DeMOS Transistors

• Published in: IEEE transactions on electron devices Vol. 60; no. 11; pp. 3827 - 3834
• Main Authors: Swain, Peeyusha Saurabha, Shrivastava, Mayank, Gossner, Harald, Baghini, Maryam Shojaei
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.11.2013; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Capacitance; Delays; Design. Technologies. Operation analysis. Testing; Device-circuit co-design; Doping; Electronics; Exact sciences and technology; Integrated circuits; Latches; Layout; level shifter (LS); Logic gates; overlap region; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; shallow trench isolation drain extended MOS (STI-DeMOS); Transistors; level shifter (LS); Trench technology; Circuit design; Low speed; Codesign; Device―circuit co-design; System on a chip; Clock; Optimization; Insulation technology; Operating rate; High voltage; Disruptive voltage; Complementary MOS technology; shallow trench isolation drain extended MOS (STI-DeMOS); Integrated circuit; overlap region; MOS transistor
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2013.2283421

This paper presents a device-circuit co-design approach to achieve a low swing, high speed 1.2-5 V level shifter (LS) using drain extended MOS (DeMOS) transistors for system on chip applications in advance CMOS technologies. Limiting factors of the high-voltage devices during transients are identified and accordingly it is shown that the maximum operating frequency of traditional LS can be increased by at least a factor of two. It is demonstrated that optimization of key device parameters of the DeMOS transistor enhances the maximum clock frequency to more than 1 GHz while preserving the device breakdown voltage and duty cycle of the level shifted signal.