Ultralow-Noise Figure and High Gain Ku-Band Bulk CMOS Low-Noise Amplifier With Large-Size Transistor

• Published in: IEEE microwave and wireless components letters Vol. 31; no. 1; pp. 60 - 63
• Main Authors: Choi, Han-Woong, Choi, Sunkyu, Kim, Choul-Young
• Format: Journal Article
• Language: English
• Published: IEEE 01.01.2021
• Subjects: Complementary metal–oxide–semiconductor (CMOS); electrostatic discharge (ESD) protection; Electrostatic discharges; Impedance matching; Inductors; Logic gates; low-noise amplifier (LNA); Noise measurement; Optimized production technology; Transistors; ultralow-noise figure
• ISSN: 1531-1309; 1558-1764
• DOI: 10.1109/LMWC.2020.3037296

This letter presents a fully integrated Ku -band low-noise amplifier (LNA) with a large-size transistor using 65-nm bulk complementary metal-oxide-semiconductor (CMOS) technology. To achieve an ultralow-noise figure, an optimization methodology balancing the ON-chip gate inductor and the parasitic capacitance of the large-size device is introduced. Using a voltage supply of 1 V, the proposed LNA has a 1.66-dB noise figure and 32.48-dB gain and, thus, outperforms other reported Ku -band bulk CMOS LNAs in these two respects. The LNA achieves the highest figure of merit I among reported Ku -band CMOS, silicon germanium, and gallium arsenide hetero-junction bipolar transistor LNAs. The LNA consumes a dc power of 22 mW and occupies a core area of <inline-formula> <tex-math notation="LaTeX">0.58\,\,{\times }\,\,0.43\,\,{\text {mm}}^{2} </tex-math></inline-formula>.