Interpreting Local Variables in AMS Assertions During Simulation

The support for local variables in SystemVerilog assertions significantly enhances its expressive power. Handling local variables in analog and mixed-signal (AMS) extensions of assertion languages is tricky due to the dense time interpretation of AMS assertions, and has not been adequately treated i...

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Bibliographic Details
Published inIEEE transactions on computer-aided design of integrated circuits and systems Vol. 38; no. 5; pp. 980 - 984
Main Authors Ain, Antara, Dasgupta, Pallab
Format Journal Article
LanguageEnglish
Published New York IEEE 01.05.2019
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Analog and mixed-signal (AMS)-assertions
Computational modeling
Integrated circuit modeling
IP networks
local variables
Mathematical models
Monitoring
Runtime
Simulation
Simulators
Trajectory
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Summary:The support for local variables in SystemVerilog assertions significantly enhances its expressive power. Handling local variables in analog and mixed-signal (AMS) extensions of assertion languages is tricky due to the dense time interpretation of AMS assertions, and has not been adequately treated in existing literature. This paper presents an approach for interpreting local variables in AMS assertions during simulation and a tool flow that works with standard mixed-mode simulators.
ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2018.2824288