Design of all pass make over based capricious digital filter using eminent speed dual carry select adder and truncation and rounding approximate multiplier for image processing application

• Published in: Concurrency and computation Vol. 35; no. 6; p. 1
• Main Authors: Mahendran, P., Kavitha, M. S., Radhika, R., Kotteeswaran, C.
• Format: Journal Article
• Language: English
• Published: Hoboken, USA John Wiley & Sons, Inc 10.03.2023; Wiley Subscription Services, Inc
• Subjects: Adding circuits; all pass makeover; capricious digital filters; Design; Digital filters; eminent speed dual carry select adder; Filter design (mathematics); Image processing; Multipliers; Power consumption; Rounding
• ISSN: 1532-0626; 1532-0634
• DOI: 10.1002/cpe.7575

Summary A design of all pass make over based capricious digital filter using eminent speed dual carry select adder and truncation based scalable rounding approximate multiplier (APM‐CDF‐ESDCSA‐TOSAM) is proposed in this article for image processing application. The proposed ESDCSA‐TOSAM is used to speed up the filter design with less area and less power consumption. In the existing designs, a carry select adder was used that was a rapid binary adders, even though, it consumes maximal area and power. For that reason, lower power, area efficient with higher speed eminent speed dual carry select adder (ESDCSA) is used in this work. The proposed ESDCSA is a fastest binary adder, which consumes less power and area. To design the ESDCSA, three blocks are used: half sum with carry generator (HSCG), final carry generator (FCG), final sum generator (FSG), these are reducing the power and area. TOSAM is used to reduce more partial products by truncating each input operands depending on its leading one‐bit position. The proposed filter is designed on Xilinx ISE 14.5 design tools. The experimental performance of the proposed filter attains lower delay 59.61%, 37.91%, 34.99%, 28.09%, 44.04% and 38.23% compared with existing filters.