Energy‐efficient system‐on‐chip reconfigurable architecture design for sum of absolute difference computation in motion estimation process of H.265/HEVC video encoding

• Published in: Concurrency and computation Vol. 34; no. 8
• Main Authors: Chandran, K.R. Sarath, Chandramani, Premanand Venkatesh
• Format: Journal Article
• Language: English
• Published: Hoboken Wiley Subscription Services, Inc 10.04.2022
• Subjects: Coders; Design; Hardware; Image processing; Matching; Mathematical analysis; motion estimation; Motion simulation; Optimization; processing elements; Reconfiguration; sum of absolute difference; system on chip; Video
• ISSN: 1532-0626; 1532-0634
• DOI: 10.1002/cpe.5461

Summary Motion estimation is the important and computationally intensive part of any video encoding. The objective of this paper is to design and analyze the coarse and fine reconfiguration of processing element‐based hardware design for block matching–based motion estimation in H.265/HEVC video processing. Sum of absolute difference (SAD) is the commonly used criteria for block matching in the motion estimation process. User input is taken as the parameter for coarse reconfiguration, and the threshold value in SAD is considered for the fine reconfiguration. Processing elements are the hardware units designed for performing SAD calculation. In this work, the hardware for block‐based motion estimation for H.265/HEVC encoder is designed using multiple processing elements, which will calculate the SAD values. A system‐on‐chip architecture is implemented and verified the optimization in terms of power and area utilization by reconfiguring the architecture dynamically based on the input video quality requirement.