Analysis of Reconfiguration Delay in Heterogeneous Systems-on-Chip via Traffic Injection

• Published in: IEEE embedded systems letters Vol. 16; no. 2; pp. 162 - 165
• Main Authors: Valente, Giacomo, Muttillo, Vittoriano, Federici, Fabio, Pomante, Luigi, Di Mascio, Tania
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 01.06.2024; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Delay; Delays; Dynamic reconfiguration; Field programmable gate arrays; field-programmable gate array (FPGA); Interference channels; Memory management; Quality of service; Random access memory; Real-time systems; Reconfiguration; System on chip; system-on-chip (SoC)
• ISSN: 1943-0663; 1943-0671
• DOI: 10.1109/LES.2023.3305401

Modern real-time systems started leveraging runtime reconfigurable architectures to reduce size, weight, and power while ensuring predictability. However, the time to reconfigure a platform (referred to as reconfiguration delay) is non-negligible and subject to fluctuations caused by conflicts in accessing shared components during the reconfiguration process. Different from existing solutions that impact either system resources or system performance, in this letter, we propose an approach, together with its supporting tools, allowing to characterize the reconfiguration delay and to be able to capture and produce evidence of the actual impact of the resource contention. In addition, we report the experiments of the proposed approach in a representative configuration on a Xilinx Zynq Ultrascale+ MPSoC; results show that conflicts can impact the reconfiguration delay at most by 230%.