All-nMOS Power-Rail ESD Clamp Circuit With Compact Area and Low Leakage

• Published in: IEEE transactions on electron devices Vol. 71; no. 9; pp. 5205 - 5211
• Main Authors: Hsieh, Chia-You, Lin, Chun-Yu
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.09.2024; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: All-nMOS; area-effective; Circuit protection; Clamps; Current mirrors; Design improvements; electrostatic discharge (ESD); Electrostatic discharge protection; Electrostatic discharges; Integrated circuits; Leakage; low leakage; Metal oxide semiconductors; Monitoring; MOS devices; Stress; Temperature measurement; Transistors
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2024.3434776

ICs are susceptible to breakage due to electrostatic discharge (ESD), making ESD protection circuits necessary for ICs. In some applications, internal circuits may adopt an all n-type transistor design. In such cases, the ESD protection circuit should only use n-type transistors to reduce the number of process masks required. This work proposes both a basic and an improved design for an all-nMOS power-rail ESD clamp. The improved design uses a current mirror circuit and nMOS string to reduce chip area and leakage, respectively. These ESD protection circuits have been implemented and validated in a 0.18-<inline-formula> <tex-math notation="LaTeX">\mu </tex-math></inline-formula> m CMOS process. The proposed designs are cost-effective and offer higher ESD robustness for practical applications.