Metal Boundary Effect Mitigation by HKMG Thermal Process Optimization in FinFET Integration Technology

• Published in: IEEE transactions on electron devices Vol. 71; no. 4; pp. 2335 - 2341
• Main Authors: Li, Zhao-Yang, Wang, Xue-Jiao, Jiang, Yu-Long
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.04.2024; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Amorphous silicon; Annealing; FinFET; FinFETs; Hafnium oxide; high-k/metal gate (HKMG); Logic gates; metal boundary effect (MBE); Molecular beam epitaxial growth; MOSFET; thermal annealing; Threshold voltage; Tin
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2024.3370119

In this work, the influence of high-<inline-formula> <tex-math notation="LaTeX">{k} </tex-math></inline-formula>/metal gate (HKMG) thermal processes such as post dielectric annealing (PDA), post metal annealing (PMA), and post amorphous Si cap annealing (PCA) on metal boundary effect (MBE) in FinFET is investigated. It is revealed that the PDA temperature increase leads to more severe MBE. On the contrary, the increase of soak or spike temperature of PMA is beneficial to reduce MBE. A higher PCA spike temperature also reduces MBE. It is demonstrated that by using an optimized combination of these three anneals, the threshold voltage (<inline-formula> <tex-math notation="LaTeX">{V}_{\text {t}}{)} </tex-math></inline-formula> shift induced by MBE can be reduced by about 50% without sacrificing device performance and reliability.