A 1.5 V 12-bit 16 MSPS CMOS Pipelined ADC with 68 dB Dynamic Range

A 1.5 V, 12-bit, 16 MSPS analog-to-digital converter was implemented in 0.25 m 1P5 M standard CMOS process with MIM capacitors. The converter achieves a peak SNDR of 66.5 dB with 5.12 MSPS and that of 63.0 dB with 16.384 MSPS. The dynamic range is 68 dB under both sampling rates. The maximum INL of...

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Bibliographic Details
Published inAnalog integrated circuits and signal processing Vol. 41; no. 2/3; pp. 269 - 278
Main Authors Liu, Ming-Huang, Ou, Wei-Yang, Su, Tsung-Yi, Huang, Kuo-Chan, Liu, Shen-Iuan
Format Journal Article
LanguageEnglish
Published 01.12.2004
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Summary:A 1.5 V, 12-bit, 16 MSPS analog-to-digital converter was implemented in 0.25 m 1P5 M standard CMOS process with MIM capacitors. The converter achieves a peak SNDR of 66.5 dB with 5.12 MSPS and that of 63.0 dB with 16.384 MSPS. The dynamic range is 68 dB under both sampling rates. The maximum INL of +/-0.8 LSB and DNL of +/-0.5 LSB were measured under 5.12 MSPS, while those of 16.384 MSPS decreased to +/-3.1 and +/-1.0 LSB, respectively. An embedded bandgap reference circuit that provides the conversion voltage range is also presented with 1.5 V supply voltage. The total power consumption of this converter was 138 mW under 16.384 MSPS or 97 mW under 5.12 MSPS. The total area of this chip is 2.8 X 2.5 mm. This chip was implemented without calibration or trimming approaches.
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ISSN:0925-1030
DOI:10.1023/B:ALOG.0000041641.72927.a9