Disturb-Free Operations of Multilevel Cell Ferroelectric FETs for Nand Applications

• Published in: IEEE transactions on electron devices Vol. 70; no. 4; pp. 1653 - 1658
• Main Authors: Jin, Chengji, Xu, Jiacheng, Gu, Jiani, Zhao, Jiayi, Jia, Xiaole, Chen, Jiajia, Liu, Huan, Zhang, Miaomiao, Peng, Yue, Chen, Bing, Cheng, Ran, Liu, Yan, Yu, Xiao, Han, Genquan
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.04.2023; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Arrays; Disturb; Electric potential; FeFETs; ferroelectric field-effect transistors (FeFETs); Ferroelectric materials; Ferroelectricity; Field effect transistors; Logic gates; multilevel cell (MLC); NAND; Pulse measurements; Semiconductor devices; Silicon; Switches; Transistors; Voltage; Voltage measurement
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2023.3242922

We have experimentally investigated disturb-free operations of multilevel cell (MLC) ferroelectric field-effect transistors (FeFETs) in a NAND array. The fabricated FeFET cells are systematically characterized, and optimized schemes to write FeFET cells into multiple states with high stability are investigated. Write and read schemes to achieve stable MLC operations of FeFET NAND arrays are proposed. For the realization of disturb-free MLC operations, both program and read disturbs are systematically characterized at the array level. In addition, margins of program inhibition voltage (<inline-formula> <tex-math notation="LaTeX">{V}_{\text {inhib}}{)} </tex-math></inline-formula> and pass voltage (<inline-formula> <tex-math notation="LaTeX">{V}_{\text {pass}}{)} </tex-math></inline-formula> are determined from the measurement results. This work provides a fundamental understanding of disturb-free MLC FeFET operations for NAND applications.