Thermal SPICE Modeling of FinFET and BEOL Considering Frequency-Dependent Transient Response, 3-D Heat Flow, Boundary/Alloy Scattering, and Interfacial Thermal Resistance
High device density and high power density intensify the self-heating effect in scaled FinFET circuits to degrade both device and back-end-of-line (BEOL) reliability. The boundary scattering in nanostructure, alloy scattering in SiGe, and interfacial thermal resistance (ITR) between different materi...
Saved in:
Published in | IEEE transactions on electron devices Vol. 66; no. 6; pp. 2710 - 2714 |
---|---|
Main Authors | , , , , |
Format | Journal Article |
Language | English |
Published |
New York
IEEE
01.06.2019
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subjects | |
Online Access | Get full text |
Cover
Loading…
Summary: | High device density and high power density intensify the self-heating effect in scaled FinFET circuits to degrade both device and back-end-of-line (BEOL) reliability. The boundary scattering in nanostructure, alloy scattering in SiGe, and interfacial thermal resistance (ITR) between different materials even worsen the self-heating. A modularized FinFET SPICE model consisting of distributed <inline-formula> <tex-math notation="LaTeX">{R} _{\textsf {th}} </tex-math></inline-formula>-<inline-formula> <tex-math notation="LaTeX">{C} _{\textsf {th}} </tex-math></inline-formula> network is used to provide a transient thermal response. A two-step pseudo isothermal plane model is proposed to characterize the thermal behavior of BEOL. Both BEOL and FinFET SPICE model are verified by TCAD simulation with dc and ac inputs. The ITR significantly raises the junction temperature of the FinFETs (<inline-formula> <tex-math notation="LaTeX">\Delta {T}_{\textsf {j}}\sim \textsf {42}~^{\circ }\text{C} </tex-math></inline-formula>). |
---|---|
ISSN: | 0018-9383 1557-9646 |
DOI: | 10.1109/TED.2019.2912426 |