Complete 3D-Reduced Surface Field Superjunction Lateral Double-Diffused MOSFET Breaking Silicon Limit

• Published in: IEEE electron device letters Vol. 36; no. 12; pp. 1348 - 1350
• Main Authors: Duan, Baoxing, Cao, Zhen, Yuan, Song, Yang, Yintang
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2015; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Breakdown voltage; LDMOS; MOS devices; MOSFET; Resistance; Silicon; Silicon Limit; SIPOS; Super Junction; silicon limit; Super junction; SIPOS; LDMOS
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2015.2493080

A new superjunction lateral double-diffused MOS with the semi-insulating poly silicon (SIPOS SJ-LDMOS) has been proposed in this letter, for the first time, with the complete three-dimensional reduced surface field (3D-RESURF). The SIPOS SJ-LDMOS along the three dimensions are subject to the electric field modulation, which achieves the complete 3D-RESURF effect. The simulated breakdown voltage (BV) for the unit length of the drift region is improved to 19.4 V/μm. The drift region with the high concentration compared with the conventional LDMOS can be depleted completely in the OFF-state to obtain the high BV. Moreover, the majority carrier accumulation can be formed to further decrease R ON,sp (specific on resistance) during the ON-state operation. Three effects have been combined to SIPOS SJ-LDMOS for the superjunction ideal, electric field modulation and the majority carrier accumulation by SIPOS. The tradeoff between the BV and R ON,sp has been improved to break through the silicon limit. The results show that the experimental R ON,sp of SIPOS SJ-LDMOS is 18 mQ · cm 2 with the tested BV of 376 V, which is less than that of 31.1 mQ · cm 2 for the N-buffer SJ-LDMOS with the simulated BV of 287 V, and far less than 71.8 mQ · cm 2 for the conventional LDMOS with the simulated BV of 254 V for the same drift region length of 20 μm.