A Ping-Pong Charge-Sharing Locking PLL With Implicit Reference Doubling and Simultaneous Frequency/Duty-Cycle Calibrations

• Published in: IEEE journal of solid-state circuits Vol. 60; no. 4; pp. 1368 - 1383
• Main Authors: Kumar, Sayan, Siriburanon, Teerachot, Dash, Sumit, Sawakewang, Patchara, Andrabi, Shuja, Strange, Jon, Muhammad, Khurram, Hung, Chih-Ming, Bogdan Staszewski, Robert
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.04.2025; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: 5G communication; Bandwidth; Calibration; Capacitors; Charge injection; charge-sharing locking (CSL); Clocks; duty-cycle calibration (DCC); Figure of merit; Frequency locked loops; frequency-tracking loop (FTL); injection locking (IL); Jitter; Locking; millimeter-wave (mmW); Oscillators; Phase locked loops; ping-pong (PP) CSL; Power demand; reference doubling; reference-frequency multiplication; Tracking; Vibration; Voltage

We propose a new ping-pong (PP) charge-sharing locking (CSL) phase-locked loop (PLL) architecture that enhances the strength of charge-injection into the oscillator's LC-tank using complementary charge-sharing capacitors during both positive and negative halves of the reference clock, effective...