A Ping-Pong Charge-Sharing Locking PLL With Implicit Reference Doubling and Simultaneous Frequency/Duty-Cycle Calibrations

• Published in: IEEE journal of solid-state circuits Vol. 60; no. 4; pp. 1368 - 1383
• Main Authors: Kumar, Sayan, Siriburanon, Teerachot, Dash, Sumit, Sawakewang, Patchara, Andrabi, Shuja, Strange, Jon, Muhammad, Khurram, Hung, Chih-Ming, Bogdan Staszewski, Robert
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.04.2025; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: 5G communication; Bandwidth; Calibration; Capacitors; Charge injection; charge-sharing locking (CSL); Clocks; duty-cycle calibration (DCC); Figure of merit; Frequency locked loops; frequency-tracking loop (FTL); injection locking (IL); Jitter; Locking; millimeter-wave (mmW); Oscillators; Phase locked loops; ping-pong (PP) CSL; Power demand; reference doubling; reference-frequency multiplication; Tracking; Vibration; Voltage
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2025.3535888

We propose a new ping-pong (PP) charge-sharing locking (CSL) phase-locked loop (PLL) architecture that enhances the strength of charge-injection into the oscillator's LC-tank using complementary charge-sharing capacitors during both positive and negative halves of the reference clock, effectively achieving an implicit <inline-formula> <tex-math notation="LaTeX">2\times </tex-math></inline-formula> reference frequency multiplication. The design includes a simultaneous frequency-tracking loop (FTL) and duty-cycle calibration (DCC) loop for robust PVT tracking, employing an ultralow-power bang-bang phase-detector (BB-PD). A class-F3 oscillator along with its third harmonic extractor generate the ~27 GHz output. Implemented in 28 nm CMOS, the PP-CSL PLL demonstrates a threefold increase in injection strength compared to the conventional CSL PLLs, while resolving the load-modulation issue and improving the reference spur by ~15 dB. It achieves an ultralow rms jitter of 42 fs with a power consumption of only 14 mW, resulting in an outstanding jitter-normalized figure of merit (<inline-formula> <tex-math notation="LaTeX">\rm FoM_{{\mathrm { jitter}}{-}N} </tex-math></inline-formula>) of −276.6 dB.