An Efficient Scheme for Acoustic Echo Canceller Implementation Using Offset Binary Coding

• Published in: IEEE transactions on instrumentation and measurement Vol. 71; pp. 1 - 14
• Main Authors: Khan, Mohd. Tasleem, Shaik, Rafi Ahamed, Alhartomi, Mohammed A.
• Format: Journal Article
• Language: English
• Published: New York IEEE 2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Acoustic cancellers; Adaptive algorithms; Adaptive filters; Application specific integrated circuits; Binary codes; Circuit design; Coding; Complexity theory; Computer architecture; Distributed arithmetic (DA); Echo cancellers; estimator; Field programmable gate arrays; Hardware; Iterative methods; least mean square (LMS); Lookup tables; Lower bounds; Mathematical analysis; Matrix algebra; Multiplication; Optimization; Random access memory; signal processing architectures; Table lookup; Throughput
• ISSN: 0018-9456; 1557-9662
• DOI: 10.1109/TIM.2021.3132087

This article presents an efficient design and implementation scheme for a low-area and low-power acoustic echo canceller. The design employs the block least mean square algorithm-based adaptive filter (ADF) using offset binary coding. The proposed approach first formulates the ADF by splitting the matrix-vector multiplication into smaller ones. Each of them is then realized with lookup tables and shift accumulate units with offset terms. An efficient scheme is suggested to update the offset terms from the corresponding lookup tables. In addition, a novel optimization scheme is proposed based on the grouping of partial products (PPs) and moving windows. The PPs are generated in two parallel styles using adders, multiplexers, and registers. The optimized architecture is shared to compute both the filter output and coefficient increment terms in every iteration. The fixed-point quantization model for the architecture is also discussed. Accuracy measure is defined to characterize the proposed design and compare it with the Cramer-Rao lower bound. Simulations are carried out to evaluate the performance of the proposed design. Field-programmable gate array implementation results and application-specific integrated circuit synthesis show that the proposed design outperforms the state-of-the-art architectures.