The Design of All-Digital Polar Transmitter Based on ADPLL and Phase Synchronized ΔΣ Modulator

• Published in: IEEE journal of solid-state circuits Vol. 47; no. 5; pp. 1154 - 1164
• Main Authors: Jian Chen, Liang Rong, Jonsson, F., Geng Yang, Li-Rong Zheng
• Format: Journal Article Conference Proceeding
• Language: English
• Published: New York, NY IEEE 01.05.2012; Institute of Electrical and Electronics Engineers
• Subjects: ADPLL; all digital; Amplifiers; Applied sciences; Circuit properties; Circuits of signal characteristics conditioning (including delay circuits); class-C DCO; class-D PA; CMOS; Delay; Delta Sigma; Design. Technologies. Operation analysis. Testing; Digital circuits; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Frequency modulation; Integrated circuits; Noise; polar transmitter; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Switches; Synchronization; Tuning; Performance evaluation; Output power; Spurious capacity; class-C DCO; Delta Sigma; Transmitter; Zero crossing; Clock; Sigma-delta modulation; CMOS; Impedance matching; Electronic packaging; class-D PA; Selector switch; Phase modulation; Phase synchronization; Phase modulator; polar transmitter; Power electronics; Oversampling; Signalling; Switching; Digital transmission; Phase locked loop; Quantization noise; Carrier frequency; Digital circuit; ADPLL; all digital; Power amplifier
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2012.2186720

An improved architecture of polar transmitter (TX) is presented. The proposed architecture is digitally-intensive and mainly composed of an all-digital PLL (ADPLL) for phase modulation, a 1-bit low-pass delta sigma ΔΣ modulator for envelop modulation, and a H-bridge class-D power amplifier (PA) for differential signaling. The ΔΣ modulator is clocked using the phase modulated RF carrier to ensure phase synchronization between the amplitude and phase path, and to guarantee the PA is switching at zero crossings of the output current. An on-chip pre-filter is used to reduce the parasitic capacitance from packages at the switch stage output. The high over sampling ratio of the ΔΣ modulator move quantization noise far away from the carrier frequency, ensuring good in-band performance and relax filter requirements. The on-chip filter also acts as impedance matching and differential to single-ended conversion. The measured digital transmitter consumes 58 mW from a 1-V supply at 6.8 dBm output power.