Row Hammer Reduction Using a Buried Insulator in a Buried Channel Array Transistor

• Published in: IEEE transactions on electron devices Vol. 69; no. 12; pp. 6710 - 6716
• Main Authors: Park, Jin Hyo, Kim, Su Yeon, Kim, Dong Young, Kim, Geon, Park, Je Won, Yoo, Sunyong, Lee, Young-Woo, Lee, Myoung Jin
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Arrays; Buried structures; Doping; Dynamic random access memory; Electric potential; Gate induced drain leakage (GIDL); Hammers; Insulators; Junctions; Leakage current; Logic gates; off current (Ioff); on current (Ion); Parameters; partial isolation type buried channel array transistor (Pi-BCAT); potential drop width (PDW); Random access memory; Reduction; row hammer effect (RHE); Semiconductor devices; Silicon; Transistors
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2022.3215931

In this article, we propose an analysis of the usage of a partial isolation type buried channel array transistor (Pi-BCAT). Compared with other structures, the conventional BCAT exhibits improved characteristics in the row hammer effect (RHE) because of its shallow drain/body (D/B) junction. Nevertheless, it remains affected by the RHE and should be mitigated because it is directly related to the reliability of dynamic random access memory (DRAM) applications. The proposed device exhibits a 50% improvement in the RHE and reduces leakage current (<inline-formula> <tex-math notation="LaTeX">{I}_{{\mathrm {OFF}}} </tex-math></inline-formula>) to one-third the level of conventional BCATs while also minimizing the ON -current (<inline-formula> <tex-math notation="LaTeX">{I}_{{\mathrm {ON}}} </tex-math></inline-formula>) reduction. Moreover, to efficiently compare RHE, we compare <inline-formula> <tex-math notation="LaTeX">\Delta {V}_{\text {SN}} </tex-math></inline-formula> by RHE and <inline-formula> <tex-math notation="LaTeX">\Delta {V}_{\text {SN}} </tex-math></inline-formula> based on the gate-induced drain leakage (GIDL) according to bias conditions and the device's parameters. Finally, we optimize the parameter values of the buried insulator by considering electrical characteristics and the RHE.