Single-Event Upset Tolerance Study of a Low-Voltage 13T Radiation-Hardened SRAM Bitcell

• Published in: IEEE transactions on nuclear science Vol. 67; no. 8; pp. 1803 - 1812
• Main Authors: Haran, Avner, Keren, Eitan, David, David, Refaeli, Nati, Giterman, Robert, Assaf, Matan, Atias, Lior, Teman, Adam, Fish, Alexander
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.08.2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: 13T bitcell; Circuits; Computer simulation; Cyclotrons; Electric potential; Heavy ions; Ion beams; Irradiation; Low voltage; Memory cells; Radiation; Radiation hardening; Radiation hardening (electronics); radiation hardening by design (RHBD); Single event upsets; single-event upset (SEU); Space applications; SRAM cells; Static random access memory; static random-access memory (SRAM); Transistors; Voltage
• ISSN: 0018-9499; 1558-1578
• DOI: 10.1109/TNS.2020.3002654

The 13T static random-access memory (SRAM) cell was designed as a low-voltage single-event upset (SEU)-tolerant device for ultralow power space applications, showing full read and write functionality down to the subthreshold voltage of 300 mV. In order to assess the SEU hardness of the device experimentally, it was tested under heavy-ion beams at the Cyclotron Resource Center, Louvain-la-Neuve, Belgium. After irradiation, bit upsets from "1" to "0" were observed, whereas bit upsets from "0" to "1" were extremely rare. Since multiple upsets occurred within addresses, we assume that in addition to random ion hits on the memory cells, the reason for the high SEU rate is ions impinging on the nonhardened peripheral circuitry. Furthermore, heavy-ion experiments and Monte Carlo simulations were performed in order to clarify the upset mechanism.