Variability Analysis for Ferroelectric FET Nonvolatile Memories Considering Random Ferroelectric-Dielectric Phase Distribution

• Published in: IEEE electron device letters Vol. 41; no. 3; pp. 369 - 372
• Main Authors: Liu, You-Sheng, Su, Pin
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.03.2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Ferroelectric field-effect transistor (FeFET); Ferroelectric materials; Ferroelectricity; Field effect transistors; Grain size; Insulators; Iron; Logic gates; memory window (MW); Nonvolatile memory; nonvolatile memory (NVM); Phase distribution; random variation; Scaling; Semiconductor devices
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2020.2967423

This paper investigates the impact of the random ferroelectric-dielectric (FE-DE) phase distribution on the memory window (MW) of the ferroelectric field-effect transistor (FeFET) nonvolatile memory (NVM) with the aid of TCAD atomistic simulations. Our study indicates that the DE path from source to drain is detrimental to the MW, and down-scaling the gate length substantially increases the probability of forming DE path and the variability in the MW. In addition, the MW variability for scaled FeFET devices can be mitigated by reducing the grain size, even under the same grain-to-channel area ratio. Besides, when down-scaling the insulator thickness to increase the MW, the increased MW variability due to the random FE-DE grains needs to be considered. Our study may provide insights for future scaling of FeFET NVMs.