Heterogeneity-Aware Scheduling on SoCs for Autonomous Vehicles

• Published in: IEEE computer architecture letters Vol. 20; no. 2; pp. 82 - 85
• Main Authors: Amarnath, Aporva, Pal, Subhankar, Kassa, Hiwot Tadese, Vega, Augusto, Buyuktosunoglu, Alper, Franke, Hubertus, Wellman, John-David, Dreslinski, Ronald, Bose, Pradip
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.07.2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Accelerators; Autonomous vehicles; design space exploration; Dynamic scheduling; Graphics processing units; Hardware; Heterogeneity; Heterogeneous SoC; Processor scheduling; Real time; real-time scheduler; Real-time systems; Space exploration; Task analysis
• ISSN: 1556-6056; 1556-6064
• DOI: 10.1109/LCA.2021.3085505

Fully autonomous vehicles (AVs) must meet stringent real-time performance and safety-criticality constraints of multiple applications simultaneously in highly dynamic environmental conditions. To enable such a system, carefully selected accelerators and general-purpose cores on Systems-on-Chips (SoCs) are required. However, schedulers that are agnostic to this heterogeneity lead to inefficient utilization of hardware resources and increase the time to complete the AV's mission. As a solution, our letter proposes a heterogeneity-aware, multi-level scheduler called HetSched. HetSched leverages run-time information about the underlying heterogeneous SoC, along with the applications' real-time constraints to improve an AV's mission time. Our evaluation demonstrates a reduction in mission time of 2.0-4.8×, when compared against state-of-the-art (SOTA) schedulers. Furthermore, when used as part of an SoC design space exploration loop, in comparison to the SOTA schedulers, HetSched reduces the number of accelerators required by an SoC to safely complete the AV's mission by 1.9× on average.