Two Transistors Voltage-Measurement-Based Test Structure for Fast MOSFET Device Mismatch Characterization

• Published in: IEEE transactions on semiconductor manufacturing Vol. 33; no. 2; pp. 166 - 173
• Main Authors: Brito, Juan Pablo Martinez, Bampi, Sergio
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.05.2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Circuits; CMOS; Current measurement; Design parameters; Electrical measurement; Linear regression; Mathematical model; Metal oxide semiconductors; MOS devices; MOSFET; MOSFETs; Regression analysis; Semiconductor device measurement; semiconductor device measurements; semiconductor device modeling; semiconductor device testing; Semiconductor devices; SPICE; Transistors; Voltage measurement
• ISSN: 0894-6507; 1558-2345
• DOI: 10.1109/TSM.2020.2988095

This work presents a test structure targeted to measure MOSFET mismatches with a fast method. It relies on two single-spot voltage measurements in order to extract <inline-formula> <tex-math notation="LaTeX">\Delta V_{TH} </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">\Delta \beta / \beta </tex-math></inline-formula> separately. The new methodology gives a theoretical increase in the measurement speed of 30x (23.17x in practice). The coefficient of determination (<inline-formula> <tex-math notation="LaTeX">R^{2} </tex-math></inline-formula>) of the linear regression analysis is used to compare standalone transistor measurements against the new proposed methodology. The correlation in the data demonstrates values not less than 0.94 (<inline-formula> <tex-math notation="LaTeX">R^{2}\geq0.94 </tex-math></inline-formula>). The test structure can reproduce parameter correlations, and it is capable of extracting MOSFET mismatch design parameters, such as Pelgrom's <inline-formula> <tex-math notation="LaTeX">A_{V_{TH}} </tex-math></inline-formula>, with an error of 2% and <inline-formula> <tex-math notation="LaTeX">A_{\beta } </tex-math></inline-formula>, with a negligible error. The experimental data presented herein are taken from measurements in prototypes fabricated in a 65nm CMOS bulk process. The whole circuit is composed of 16 2D addressable DUT device matrices, each having 256 same-size closely-placed MOSFET devices, totaling 4,096 MOS devices used in single-type (NMOS) transistor array.