A New Low-Capacitance High-Voltage-Tolerant Protection Clamp for High-Speed Applications

A new low-capacitance clamp is introduced for high-voltage-tolerant and high-speed interface applications. An embedded stacking architecture is proposed to address latch-up-immune design requirements without degradation in the electrostatic discharge (ESD) stress-handling capability, leakage, or cap...

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Bibliographic Details
Published inIEEE transactions on electron devices Vol. 67; no. 8; pp. 3030 - 3034
Main Authors He, Linfeng, Salcedo, Javier A., Parthasarathy, Srivatsan, Hajjar, Jean-Jacques, Sundaram, Kalpathy
Format Journal Article
LanguageEnglish
Published New York IEEE 01.08.2020
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Capacitance
Clamps
CMOS
Computer architecture
Electrostatic discharge (ESD)
Electrostatic discharges
High speed
High voltages
high-definition multimedia interface
high-voltage-tolerant interface protection
holding-voltage modulation
Latch-up
Microprocessors
Resistors
Static electricity
Threshold currents
Topology
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Summary:A new low-capacitance clamp is introduced for high-voltage-tolerant and high-speed interface applications. An embedded stacking architecture is proposed to address latch-up-immune design requirements without degradation in the electrostatic discharge (ESD) stress-handling capability, leakage, or capacitance. Thanks to a parallel current conduction path activated during ESD stress, a state-of-the-art failure threshold current per unit area is obtained for high-voltage-tolerant interface applications in sub-28-nm CMOS process technologies. The device design concept introduced in this article facilitates the implementation of compact, high-performance interface applications, extended in general to protection clamp devices requiring a higher holding voltage.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2020.3002877