Fast Montgomery Modular Multiplier Using FPGAs

• Published in: IEEE embedded systems letters Vol. 14; no. 1; pp. 19 - 22
• Main Authors: Pajuelo-Holguera, Francisco, Granado-Criado, Jose M., Gomez-Pulido, Juan A.
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 01.03.2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adders; Algorithms; Cryptography; Encryption; Field programmable gate arrays; field-programmable gate array (FPGA); High level synthesis; high-level synthesis (HLS); Montgomery modular multiplication; Multiplication; parallelism; Performance enhancement; Performance evaluation; Proposals; Software; VHDL

This letter details a fast and efficient implementation of the Montgomery modular multiplication by taking advantage of parallel multipliers and adders. This implementation was programmed in high-level synthesis language and tested on a field-programmable gate array device. In order to test the perf...