Fast Montgomery Modular Multiplier Using FPGAs

This letter details a fast and efficient implementation of the Montgomery modular multiplication by taking advantage of parallel multipliers and adders. This implementation was programmed in high-level synthesis language and tested on a field-programmable gate array device. In order to test the perf...

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Bibliographic Details
Published inIEEE embedded systems letters Vol. 14; no. 1; pp. 19 - 22
Main Authors Pajuelo-Holguera, Francisco, Granado-Criado, Jose M., Gomez-Pulido, Juan A.
Format Journal Article
LanguageEnglish
Published Piscataway IEEE 01.03.2022
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Adders
Algorithms
Cryptography
Encryption
Field programmable gate arrays
field-programmable gate array (FPGA)
High level synthesis
high-level synthesis (HLS)
Montgomery modular multiplication
Multiplication
parallelism
Performance enhancement
Performance evaluation
Proposals
Software
VHDL
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Summary:This letter details a fast and efficient implementation of the Montgomery modular multiplication by taking advantage of parallel multipliers and adders. This implementation was programmed in high-level synthesis language and tested on a field-programmable gate array device. In order to test the performance of the proposal, a sequential version of the algorithm was also implemented in hardware. Moreover, we compared the parallel implementation with a software version and with five contributions from the literature. This way, we found that our proposal improves the performance of all other implementations.
ISSN:1943-0663
1943-0671
DOI:10.1109/LES.2021.3090029