Iterative Inter-Cell Interference Cancellation Receiver for LDPC-Coded MIMO Systems

• Published in: IEEE transactions on signal processing Vol. 67; no. 6; pp. 1636 - 1647
• Main Authors: Sun, Wei-Cheng, Chen, Yan-Tong, Yang, Chia-Hsiang, Ueng, Yeong-Luh
• Format: Journal Article
• Language: English
• Published: New York IEEE 15.03.2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Cancellation; CMOS; Codes; Computer architecture; Decoding; Detectors; digital CMOS integrated circuits; Digital computers; Error correcting codes; Error detection; Inter-cell interference (ICI) cancellation; Interference; Iterative methods; Likelihood ratio; low-density parity-check (LDPC) code; MIMO (control systems); MIMO communication; multiple-input multiple-output (MIMO); Parity check codes; Receivers; Sensors; State of the art
• ISSN: 1053-587X; 1941-0476
• DOI: 10.1109/TSP.2019.2894776

In an ultra-dense cellular system, users at the cell-edge are susceptible to inter-cell interference (ICI) because of the overlap of the spectrum. To combat ICI, this paper investigates two iterative ICI cancellation approaches for low-density parity-check-coded multiple-input multiple-output systems. One approach includes separate signal and interference detectors; the other one employs a joint detector for both the desired signal and interference. The joint-detector approach achieves a comparable error-rate performance with only half the computational complexity when compared to the separate-detector counterpart. An iterative ICI cancellation receiver using the joint detector is proposed and implemented. Its hardware efficiency is significantly enhanced by leveraging an efficient coordinate rotation digital computer based processing array, an adaptive input-range scaling scheme, and an area-efficient log-likelihood ratio calculator. The iterative ICI cancellation receiver is flexible enough to support multiple modulations of up to 256-QAM. The maximum gross throughput is 1.24 Gb/s for a 4×4 256-QAM configuration in a 40-nm CMOS technology. The proposed iterative receiver outperforms the current state-of-the-art works in both the throughput-to-area ratio and the normalized energy metrics, despite the added ICI capability.