A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth

This paper describes a 32-bank 1 Gb DRAM achieving 1 Gbyte/s (500 Mb/s/DQ pin) data bandwidth and the access time from RAS of 31 ns at V/sub cc/=2.0 V and 25/spl deg/C. The chip employs (1) a merged multibank architecture to minimize die area; (2) an extended small swing read operation and a single...

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Published inIEEE journal of solid-state circuits Vol. 31; no. 11; pp. 1635 - 1644
Main Authors Yoo, Jei-Hwan, Kim, Chang-Hyun, Lee, Kyu-Chan, Kyung, Kye-Hyun, Yoo, Seung-Moon, Lee, Jung-Hwa, Son, Moon-Hae, Han, Jin-Man, Kang, Bok-Moon, Haq, Ejaz, Lee, Sang-Bo, Sim, Jai-Hoon, Kim, Joung-Ho, Moon, Byung-Sik, Kim, Keum-Yong, Park, Jae-Gwan, Lee, Kyu-Phil, Lee, Kang-Yoon, Kim, Ki-Nam
Format Journal Article
LanguageEnglish
Published IEEE 01.11.1996
Subjects
Bandwidth
Circuits
Clocks
Delay
Energy consumption
Frequency
Moon
Multiprocessing systems
Random access memory
Registers
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Summary:This paper describes a 32-bank 1 Gb DRAM achieving 1 Gbyte/s (500 Mb/s/DQ pin) data bandwidth and the access time from RAS of 31 ns at V/sub cc/=2.0 V and 25/spl deg/C. The chip employs (1) a merged multibank architecture to minimize die area; (2) an extended small swing read operation and a single I/O line driving write scheme to reduce power consumption; (3) a self-strobing I/O schemes to achieve high bandwidth with low power dissipation; and (4) a block redundancy scheme with increased flexibility. The nonstitched chip with an area of 652 mm/sup 2/ has been fabricated using 0.16 /spl mu/m four-poly, four-metal CMOS process technology.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.1996.542308