Stream Processing Architectures for Continuous ECG Monitoring Using Subsampling- Based Classifiers

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 32; no. 1; pp. 68 - 78
• Main Authors: Loh, Johnson, Gemmeke, Tobias
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.01.2024; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Accelerators; Algorithms; Application specific integrated circuits; Application-specific integrated circuit (ASIC); Artificial neural networks; Biomedical data; Biomedical monitoring; Circuit design; Classification; Classifiers; Co-design; Complexity; Data transmission; design constraints; design space exploration; electrocardiogram (ECG) processing; Electrocardiography; Hardware; Low-power electronics; Monitoring; Neural networks; Power consumption; streaming architecture; Streaming media; ultralow power
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2023.3329360

Monitoring of biomedical data, such as electrocardiogram (ECG) signals, requires accelerators, which can process data streams in a continuous manner. Especially, wearable monitoring systems require both ultralow power consumption and sufficiently complex deep neural network (DNN) classifiers to identify asymptomatic and critical health conditions, such as atrial fibrillation (AF). Such continuous data streams pose unique constraints on the processing pipeline for classification systems, which can be addressed in the design methodology of application-specific integrated circuits (ASICs). In this work, we identify specific constraints to define common operating conditions, which guide the design of ECG accelerators in an algorithm-hardware codesign methodology. In specific, we show that the input frame size and the number of classifications per time frame play a significant role for the computational complexity (CC) of the classifier, as well as the ECG accelerator executing the classifier in a continuous manner. As an example, the constraints are applied in a top-down algorithm-hardware codesign flow. Here, an ECG accelerator is designed starting from an AF classifier, while proposed constraints are considered in an early design stage to estimate costs for the hardware design. In the end, it is essential for future ECG accelerators to adhere to common constraints in the design process to handle increasingly complex DNN classifiers for continuous data streams with ultralow power targets.