A New Etch Planarization Technology to Correct Non-Uniformity Post Chemical Mechanical Polishing

• Published in: IEEE transactions on semiconductor manufacturing Vol. 28; no. 4; pp. 502 - 507
• Main Authors: Meihua Shen, Baosuo Zhou, Yifeng Zhou, Hoang, John, Bowers, Jim, Bailey, Andrew D., Pape, Eric, Singh, Harmeet, Wise, Rich, Dasaka, Ravi K.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.11.2015; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: CMP non-uniformity; etch; etch correction; Fabrication; Planarization; Semiconductor device manufacture; Sensitivity; temperature sensitivity; Thin films; planarization; etch; CMP non-uniformity; etch correction; temperature sensitivity
• ISSN: 0894-6507; 1558-2345
• DOI: 10.1109/TSM.2015.2477718

The introduction of 3-D structures and new materials for advanced logic devices at extremely fine feature size presents challenges for within-wafer and wafer-to-wafer thickness uniformity control that is critical for yield and performance. For conventional chemical mechanical polishing technology, the typical thin film uniformity across the whole wafer may not meet the desired variation target of 2-3 nm 3σ at some critical levels. Furthermore, wafer-to-wafer uniformity variation requires a wafer by wafer approach to uniformity correction. In this paper, a novel etch planarization technology is presented that combines a conventional production-proven etch process that is temperature sensitive with an inductively coupled plasma reactor equipped with a novel electrostatic chuck that provides die level thermal control. Improved process control enables cost effective uniformity improvements in excess of 85%.