A Classification of Memory-Centric Computing

• Published in: ACM journal on emerging technologies in computing systems Vol. 16; no. 2; pp. 1 - 26
• Main Authors: Nguyen, Hoang Anh Du, Yu, Jintao, Lebdeh, Muath Abu, Taouil, Mottaqiallah, Hamdioui, Said, Catthoor, Francky
• Format: Journal Article
• Language: English
• Published: 30.04.2020
• ISSN: 1550-4832; 1550-4840
• DOI: 10.1145/3365837

Technological and architectural improvements have been constantly required to sustain the demand of faster and cheaper computers. However, CMOS down-scaling is suffering from three technology walls: leakage wall, reliability wall, and cost wall. On top of that, a performance increase due to architectural improvements is also gradually saturating due to three well-known architecture walls: memory wall, power wall, and instruction-level parallelism (ILP) wall. Hence, a lot of research is focusing on proposing and developing new technologies and architectures. In this article, we present a comprehensive classification of memory-centric computing architectures; it is based on three metrics: computation location, level of parallelism, and used memory technology. The classification not only provides an overview of existing architectures with their pros and cons but also unifies the terminology that uniquely identifies these architectures and highlights the potential future architectures that can be further explored. Hence, it sets up a direction for future research in the field.