Design of Poly-Si Junctionless Fin-Channel FET With Quantum-Mechanical Drift-Diffusion Models for Sub-10-nm Technology Nodes

• Published in: IEEE transactions on electron devices Vol. 63; no. 12; pp. 4610 - 4616
• Main Authors: Lee, Junsoo, Kim, Youngmin, Cho, Seongjae
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2016; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: CMOS technology; Cost-effective process integration; Current leakage; Doping; Drift; Field effect transistors; FinFET; FinFETs; high- kappa /metal gate technology; junctionless field-effect transistor (JLFET); Leakage current; Performance degradation; polycrystalline-silicon (poly-Si) channel; Polysilicon; quantum-mechanical drift-diffusion models; Semiconductor device modeling; Silicon; Silicon substrates; SOI (semiconductors); sub-10-nm Si CMOS technology; Substrates; Work functions
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2016.2614990

In this paper, a junctionless FinFET (JLFinFET) having polycrystalline-silicon (poly-Si) channel has been optimally designed and characterized by stringent device simulation aiming 10-nm-and-beyond Si technology node. Replacing the silicon-on-insulator platform employed for realizing the JLFETs in most cases by bulk Si substrate featuring deposited oxide and poly-Si channel would warrant highly cost-effective process integration. Here, the high-κ/metal-gate technology is also adopted to enhance the gate controllability, prevent the gate leakage current, and obtain appropriate gate work function. It is demonstrated from the device simulation results with higher accuracy and credibility by multiple models, particularly including the quantum-mechanical models in drift and diffusion conductions that the poly-Si JL FinFET has the strong potential for the 10-nm-and-beyond Si CMOS technology with little performance degradation in comparison with the JL FinFET with crystalline Si channel.