A Semi-Supervised and Incremental Modeling Framework for Wafer Map Classification

• Published in: IEEE transactions on semiconductor manufacturing Vol. 33; no. 1; pp. 62 - 71
• Main Authors: Kong, Yuting, Ni, Dong
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.02.2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Acceleration; Artificial neural networks; Classification; Decoding; Feature extraction; ladder network; Learning curves; Manufacturing; Noise reduction; Quality control; semi-supervised classification; Semiconductor device modeling; semiconductor manufacturing; Unsupervised learning; variational autoencoder; Wafer map
• ISSN: 0894-6507; 1558-2345
• DOI: 10.1109/TSM.2020.2964581

Wafer map analysis provides critical information for quality control and yield improvement tasks in semiconductor manufacturing. In particular, wafer patterns of gross failing areas (GFA) are important clues to identify the causes of relevant failures during the manufacturing process. In this work, a semi-supervised classification framework is proposed for wafer map analysis, and its application to wafer bin maps with GFA patterns classification is demonstrated. The Ladder network and the semi-supervised variational autoencoder are adopted to classify wafer bin maps in comparison with a standard convolutional neural network (CNN) model on two real-world datasets. The results have illustrated that two semi-supervised models are consistently and substantially better than the CNN model across various training data percentages by effective utilization of the unlabeled data. Active learning and pseudo labeling are also utilized to accelerate the learning curve.