Asymmetric Gate Schottky-Barrier Graphene Nanoribbon FETs for Low-Power Design

• Published in: IEEE transactions on electron devices Vol. 61; no. 12; pp. 4000 - 4006
• Main Authors: Gholipour, Morteza, Masoumi, Nasser, Chen, Ying-Yu Christine, Deming Chen, Pourfath, Mahdi
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2014; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Asymmetric gate (AG); Graphene; graphene nanoribbon field-effect transistor (GNRFET); Integrated circuit modeling; Inverters; Logic gates; Photonic band gap; Schottky-barrier (SB); Semiconductors; Simulation; SPICE; Tunneling; Asymmetric gate (AG); Schottky-barrier (SB); graphene nanoribbon field-effect transistor (GNRFET)
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2014.2362774

The ambipolar behavior limits the performance of Schottky-barrier-type graphene nanoribbon field-effect transistors (SB-GNRFETs). We propose an asymmetric gate (AG) design for SB-GNRFETs, and show that it can significantly reduce the IOFF. Simulation results indicate at least 40% and 5× improvement in the subthreshold swing and the I ON /I OFF ratio, respectively. We build an accurate semianalytical closed-form model for the current-voltage characteristics of SB-GNRFETs. The proposed Simulation Program with Integrated Circuit Emphasis (SPICE)-compatible model considering various design parameters and process variation effects, which enables efficient circuit-level simulations of SB-GNRFET-based circuits. Simulation results of benchmark circuits show that the average energy-delay product of the AG SB-GNRFETs is only ~22% of that of a symmetric gate for the ideal case and ~88% for devices with line edge roughness.