Analysis of interface trap density and channel mobility in 4H-SiC NMOS capacitors and lateral MOSFETs

• Published in: 2016 European Conference on Silicon Carbide & Related Materials (ECSCRM) Vol. 897; p. 1
• Main Authors: Domeij, M., Franchi, J., Gumaelius, K., Lee, K., Allerstam, F.
• Format: Conference Proceeding Journal Article
• Language: English
• Published: Pfaffikon Trans Tech Publications Ltd 15.05.2017
• Subjects: Capacitance-voltage characteristics; Capacitors; Density; D|T extraction; Frequency measurement; high-low method; Logic gates; Metal oxide semiconductors; MOSFET; MOSFETs; SiC MOSFET; Silicon carbide; subthreshold slope; Threshold voltage; Subthreshold Slope; High-Low Method; SiC MOSFET; DIT Extraction
• ISSN: 1662-9752; 0255-5476; 1662-9752
• DOI: 10.4028/www.scientific.net/MSF.897.115

Lateral implanted SiC MOSFETs and NMOS capacitors were fabricated and used to extract channel mobility and interface state density D IT for three different gate oxides. D IT values were extracted using the high(1 MHz)-low(1 kHz) method for NMOS capacitors and the subthreshold slope for MOSFETs. The subthreshold slope extraction gave 6-20 times higher D IT values compared to the high-low method, presumably because the high-low method cannot capture the fastest traps [1]. None of the methods resulted in clear proportionality between the inverse channel mobility and D IT . The subthreshold slope gave similar D IT values for samples with different surface p-doping concentrations indicating that the method is not sensitive to the threshold voltage.