A vertical FET with self-aligned ion-implanted source and gate regions

A new self-aligned vertical channel JFET has been fabricated using ion-implantation and LOCOS techniques. This device required four photolithography processes. Fine patterning and accurate mask alignment are not required by this process. The electrical properties of this device are a voltage amplifi...

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Bibliographic Details
Published inIEEE transactions on electron devices Vol. 25; no. 1; pp. 56 - 57
Main Authors Ozawa, O., Iwasaki, H.
Format Journal Article
LanguageEnglish
Published IEEE 01.01.1978
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Summary:A new self-aligned vertical channel JFET has been fabricated using ion-implantation and LOCOS techniques. This device required four photolithography processes. Fine patterning and accurate mask alignment are not required by this process. The electrical properties of this device are a voltage amplification factor of more than 5, a source-to-gate breakdown voltage of 50 V, and a drain-to-gate breakdown voltage of 140 V. It is possible to realize a larger voltage amplification factor, compared to the diffused vertical FET.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
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content type line 23
ISSN:0018-9383
1557-9646
DOI:10.1109/T-ED.1978.19031